1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly to a technology for reducing current consumption of a semiconductor chip.
2. Related Art
Along with increasing integration of semiconductor memory devices, semiconductor memory devices have been continuously improved to increase operation speed thereof. In order to increase operation speeds of semiconductor memory devices, synchronous memory devices capable of operating by synchronizing with an external clock of a memory chip have recently been proposed and developed.
A representative example of a synchronous memory device is a single data rate (SDR) synchronous memory device. A SDR synchronous memory device is synchronized with a rising edge of an external clock of a memory device such that one data piece can be input and/or output at one data pin during one period of the clock.
However, the SDR synchronous memory device has difficulty in satisfying high-speed system operations.
In order to solve the problem of the SDR synchronous memory device, a double data rate (DDR) synchronous memory device capable of processing two pieces of data during one clock period has been proposed.
Two contiguous pieces of data are input and output through respective data input/output (I/O) pins of the DDR synchronous memory device, such that the two contiguous pieces of data are synchronized with a rising edge and a falling edge of an external input clock.
Therefore, although a clock frequency of the DDR synchronous memory device is not increased, the DDR synchronous memory device may have a bandwidth that is at least two times larger than that of the SDR synchronous memory device. Therefore, the DDR synchronous memory device can operate at a higher speed than the SDR synchronous memory device.
The semiconductor memory device has a plurality of banks. The banks are configured to increase a page hit rate as well as to increase the efficiency of a memory bus. If the memory device having multiple banks receives a control command from the external part, a drive control device of the memory device generates various control signals needed for the corresponding operation. The control signals are then transmitted to divided cell arrays (i.e., individual banks).
The data processing operations of the memory device are as follows.
First, a row address is applied to the semiconductor memory device in such a manner that the semiconductor memory device accesses a cell array matrix.
If the row address is applied to the semiconductor memory device the corresponding word line is activated, resulting in implementation of the sensing operation.
Therefore, data is read from or written in the cell designated upon receiving a column address.
If the memory device having multiple banks activates many banks within a window of a predetermined time, excessive current consumption may occur. Therefore, many developers or manufacturers of semiconductor memory devices have made efforts to reduce current consumption of the memory device having multiple banks.